This project will be made of multiple parts. First, I'll explain the basics of designing a differential probe then the following posts will be about how to actually do the math and lay out the PCB for something like this.
But first thing's first:
"Excuse me, how much is this?"
Have you ever wondered why are differential oscilloscope probes so expensive? Well, I have, and the answer is....out there?!
No, seriously, I would accept a price of 100 to 150 Euros for a probe, maybe even 200 Euros, but anything over this seems like a waste of money, considering what these devices have inside them (we'll get into this a bit later). Also, some manufacturers just re-brand probes as their own and add an extra 50-100 Euros just because it has some fancy well known T.E. manufacturer logo on it.
Lately, the prices on eBay have jumped to some ludicrous amounts just because the sellers think they have the market cornered. Of course. they're just being stupid.
So, WHAT are these things made of?
For starters, an input attenuation stage which is nothing more than a compensated resistive divider (one divider for the positive and negative input) followed by a differential amplifier. Simple, right?. The input attenuation stage is designed either with two high voltage resistors and two caps in parallel, or multiple lower voltage rated resistors.
After the input signal has been divided down to a reasonable level, a differential stage comes next. This rejects the common mode noise and does some amplification, if needed, then this passes it on to the next stage, where differential to single-ended conversion takes place.
This will be the actual signal that your oscilloscope sees. Follow this by an optional output stage, if you need that 50 Ohms matching impedance, and that's all.
It may sound complicated, but there's really nothing to it. You could build one for 30 or 40 Euros, designed either for high voltage (1KV to 2KV) and low bandwidth (about 20 MHz) or lower voltage but higher bandwidth (up to 1GHz). For the latter, the design shown here : https://xellers.wordpress.com/electronics/1ghz-active-differential-probe/ is relatively simple, inexpensive and very useful. It'll go up to 1Ghz bandwidth and -20dB attenuation which is all most people ever need in their prjects.
I wanted, as an exercise, to design and build a high voltage probe, capable of taking in a differential signal of up to 1.5 KV and with a bandwidth of somewhere around 15-20 MHz. Also it must have variable attenuation (1/10 and 1/100 or 1/50 and 1/500) and be powered from a 9 Volt battery - this last part is to make sure there isn't going to be any ground loops that can ruin your day and also it makes shielding the whole circuit much easier. Most importantly, it should cost below 50 Euros in parts (does not include the PCB, if I decided to have one made and not go DIY on this).
For starters, I took an already existing design then replicate that so to keep the costs down. K.I.S.S. right?
I searched for a schematic (easier said than done) of an existing commercial differential probe then took that as a scaffolding for my design.
I managed to track down a schematic on this site: http://www.diyaudio.com/forums/equipment-tools/248505-differential-probe-reverese-engineered.html which together with with the teardown pictures from here, gave me a pretty good idea of how to go about building the probe.
For anyone trying to do the same, or just and make sense of the schematics from the above link, some values for components are not the right ones. I got some values by cross-referencing the schematic to the actual photos of the probe. What values I could't find at all, I calculated them or mucked around in LT Spice until I got a satisfactory response from the circuit.
This is my first project where I'm working with frequencies above 1 MHz, so bare with me here.
"So I want to build a High Voltage differential probe. Ho do I do this?"
This is where the real magic happens. Once I had the general idea behind these probes, I got down to the nitty-gritty. Although the input stage is the first one an input signal sees, I started off with the differential amplifier.
The schematics in the previous links don't make much sense, so let me put things into perspective:
Looks friendlier now, doesn't it? Now let's see how this thing works. It's basically just a JFET differential amplifier with some bits stuck to it to make the thing behave better from DC all the way to a couple of MHz. The guts of this thing is the matched JFET pair Q4A and Q4B. For those who are just getting to grips with electronics, matched means that both of these transistors are housed in the same package so as the noise and temperature affects them in the same manner and you don't get an imbalance in the amplifier.
"So, why don't I just stick the output from the input attenuation stage into an op-am instead of reading this long post? "
Well, I'm glad you asked. Thing is, you want a very high impedance at the input of this probe. Sure, you might have a few resistors of a couple of MegaOhms on the input, isn't that enough? Nope, The more the better. But the bigger the input impedance, the bigger the gain-setting resistors will have to be. And those values, together of the capacitance of the input of your op-amp will make a low pass filter which will slow down the op-amp itself. And when you want to go into the 10-20 MHz region, that just won't cut it.
"Then, how about we buffer the input with a few more op-amps?"
Yes...and No. You could, but you'd need some high speed op-amps, to form an "instrumentation amplifier" design:
But high speed op-amps are expensive. Also you don't just stick the output of an op-amp into the input of another at high frequencies, because they tend to oscillate and do all kinds of other unpleasant things.
OK, if you actually go and try this with three op-amps that have a bandwidth of, say, 200 to 500 MHz (I'm talking about the Gain-Bandwidth Product here), odds are it will do the business.
But there is another factor to take into consideration. Common Mode Rejection. Remember that you'll be measuring differential voltages with this probe. Meaning, you can stick the negative terminal of the probe anywhere in the circuit and measure THAT relative to the Positive one. But that Negative terminal can sometimes be at a potential that is not Ground. It can be at a potential of +150 Volts and the Positive at +300 Volts. So you'll be measuring +150 Volts, but that signal will be piggy-backing on top of another 150 volts from ground, which your probe will have to ignore.
How does it do that? With a high Common Mode Rejection Ratio (CMRR).
The three op-amps previously talked about will most likely work, but the low CMRR of the design will let you only measure voltages that are near Ground potential. (a few tens of volts, maybe a hundred or two, depends on your choice of op-amp). Most op-amps tend to have a CMRR that drops the further up in frequency and gain you go.
Sorry for the long detour, but this was needed to explain the whole idea why a JFET differential input should be used (at least in my case).
Now back to the story.
"So, we're going to be using the JFETs. What do the rest of the things in the circuit ACTUALLY do?"
Another fine question. So, starting from the top, R13 and R24 are drain resistors that set the gain of our differential stage. The gain will be G = gm*RD where gm is the transconductance of the JFETs and RD is the value of R13 = R24 (the drain resistors).
Now, because JFETs usually have a very low transconductance, that means that the gain will be relatively small. No big deal you say? Well, remember the probe will be a selectable 1/10 and 1/100 one, so at some point, you will need to step up the gain so you can measure small signals (tens of volts), not just whopping big Kilo-volt signals.
To step up the gain, you could just increase the Drain resistors, but that will limit the current through the JFETs. Also, you can't whack in just any resistors. Resistors have a tolerance rating and also a temperature coefficient. Because the JFET pair is matched, you'll need matching drain resistors also. "Matched" meaning they'll have to behave the same, so 1% or better tolerance resistors are needed and a temperature coefficient as low as possible is also a must (50ppm or less). But that means more money.
So another trick would be to increase the transconductance of the FETs and that's what Q5B-R17 and Q5C-R35 are doing.
Their role is twofold: first, they provide a somewhat constant current (they sink current) of VBE/RB and second, they provide a low impedance output. The Base resistors will have to be well matched and also their value set for the particular FET one might use i.e. match the current sink to the value of IDSS. And even so, in some cases, the drain current will still vary with temperature, so I'll have to see if I leave things as they are now.
So, let's say that each leg of the differential amp sinks a current of 2 mA (that's 1mA for the Q4A/B and 1mA for Q5B/C), that means the current sink in the tail of the differential amplifier will sink a total of 4mA. Q5 Q6 amd Q7 make up a Wilson current mirror, with the current established by Q8. Diode D1 is actually a LED which will provide the base current for Q8.
Now, of course, this circuit does have some drawbacks, the main one being the power supply voltage. For example, if the whole thing will be powered directly from some batteries (a 9 volt one maybe), the positive rail will inevitably go down, taking the current through R13/R24 with it. This will cause the whole circuit to go berserk.
To resolve this issue, one could swap out the BJTs in the source of the JFETs with PNP transistors, this time connected to the drain. This configuration will give a stable drain current, regardless (within reasonable values of voltage drop, of course) of how much the positive rail sags.
I've done some simulations in LT Spice and noticed that the configuration with the NPNs in the Source has a flat bandwidth response to about 22-25 MHz and the one with the PNPs only goes to about 1 MHz or so and also very hard to tweak it to get it to have the right gain AND response.
This is with the NPN BJTs in the Source of the JFETs
This is with the PNP BJTs in the Drain of the JFETs
So, I think I'll go with the configuration that has the NPNs in the Source, just like it is on the commercial probes. It's going to be battery powered, with a DC-DC converter that 's going to give me the +9 and -9 volts rails and hopefully not be bothered pretty much by that positive rail voltage sagging issue.
In the next post, I will give some more details about how the circuit behaves in the simulations and show how to choose the right JFETs and other components.
Their role is twofold: first, they provide a somewhat constant current (they sink current) of VBE/RB and second, they provide a low impedance output. The Base resistors will have to be well matched and also their value set for the particular FET one might use i.e. match the current sink to the value of IDSS. And even so, in some cases, the drain current will still vary with temperature, so I'll have to see if I leave things as they are now.
So, let's say that each leg of the differential amp sinks a current of 2 mA (that's 1mA for the Q4A/B and 1mA for Q5B/C), that means the current sink in the tail of the differential amplifier will sink a total of 4mA. Q5 Q6 amd Q7 make up a Wilson current mirror, with the current established by Q8. Diode D1 is actually a LED which will provide the base current for Q8.
Now, of course, this circuit does have some drawbacks, the main one being the power supply voltage. For example, if the whole thing will be powered directly from some batteries (a 9 volt one maybe), the positive rail will inevitably go down, taking the current through R13/R24 with it. This will cause the whole circuit to go berserk.
To resolve this issue, one could swap out the BJTs in the source of the JFETs with PNP transistors, this time connected to the drain. This configuration will give a stable drain current, regardless (within reasonable values of voltage drop, of course) of how much the positive rail sags.
I've done some simulations in LT Spice and noticed that the configuration with the NPNs in the Source has a flat bandwidth response to about 22-25 MHz and the one with the PNPs only goes to about 1 MHz or so and also very hard to tweak it to get it to have the right gain AND response.
So, I think I'll go with the configuration that has the NPNs in the Source, just like it is on the commercial probes. It's going to be battery powered, with a DC-DC converter that 's going to give me the +9 and -9 volts rails and hopefully not be bothered pretty much by that positive rail voltage sagging issue.
In the next post, I will give some more details about how the circuit behaves in the simulations and show how to choose the right JFETs and other components.
For anyone interested in this subject and/or those searching for inspiration, the following links may be of some use:
- http://www.eevblog.com/forum/projects/oshw-diy-1kv-100mhz-differential-probe-(dilemma-vs-hope)/
- http://www.dgkelectronics.com/high-voltage-differential-probe/
Later edit:
Thank you Marko for spotting my mistake in the initial schematic of the probe. I wanted to redo this for quite some time...looks like this is a good a time as any.
Thank you Marko for spotting my mistake in the initial schematic of the probe. I wanted to redo this for quite some time...looks like this is a good a time as any.
The output from the JFET buffer is now taken from the Drain instead of the Source, like I initially did.
However, this is not quite satisfactory to me. Simulations and common sense and also some more reading on the matter lead me to believe that the initial reverse engineered schematic might be wrong.
My initial hunch was that the schematic with Q4A, Q4B, Q5B and Q5C formed a complementary feedback pair. But the original schematic showed NPNs for Q5. Something did not add up.
So, from this, two conclusions may emerge:
- if indeed Q5 A and B are NPN, the they don't form a CFP with the FETs. The only other explanation that comes to my mind is that they rather serve as a current source for the FETs. That sounds plausible, but that means that whoever did the reverse engineering goofed, which is kinda' hard to believe.
- however, were they to form a CFP, Q5 A and B would have to be PNPs, thus resulting in this schematic:
This is not much different from the initial one.
I will do some proper investigation in the future to see what configuration actually behaves better, but for now, this will have to do, as I do not posess the gear to confirm or infirm any results from SPICE simulations.
